The present invention relates to a method for manufacturing a semiconductor device, which can reduce or prevent the warpage of a substrate in the manufacture of a semiconductor device so that the warpage of a chip can be suppressed even without modifying a packaging process, thereby preventing a defective package from being caused.
In general, a wafer, in which memory devices are formed, is sawn into chips which in turn are packaged through a packaging process. In the packaging process, the degree of warpage present in the chip can cause a defective package due to, for example, a wire bonding failure or a die lifting phenomenon upon stacking multiple chips.
In order to enable the packaging process, the back surface of a wafer is first grinded by a preset thickness. At this time, warpage markedly occurs on the front surface of the wafer. This results from the fact that, after conducting a multi-layered metal line forming process using a metal line material having high tensile stress, such as aluminum (Al) and tungsten (W), and depositing a passivation layer, when conducting an annealing process, the compressive stress of insulation layers is considerably removed, and tensile stress exists in the wafer.
In the conventional art, if a wire bonding failure in a chip package or a die lifting phenomenon in a stack package occurs due to the warpage of a chip or chips, high bonding force is applied in the packaging process or die attachment parameters on the package are changed. However, these methods result in the deterioration of the packaging efficiency and the extension of a processing time.